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[ELanguage] rs(31-19)

Description: 本源代码是RS（31,19）编码器的顶端实现程序和测试程序，此程序可以验证编码器工作与否。此代码，已在ModelSim验证通过。并附上测试时所产生的结果图像。-Source code is RS (31,19) encoder to achieve the top programs and testing procedures, this program can verify the encoder to work or not. This code has been verified in ModelSim. Together with the result when the test images.
Platform: | Size: 376832 | Author: jianghong | Hits:

[VHDL-FPGA-Verilog] PPM_Coder

Description: PPM 编码器 按照PPM编码格式编写的普通VHDL代码-PPM PPM encoder encoding format prepared in accordance with the ordinary VHDL code
Platform: | Size: 1024 | Author: newly | Hits:

[VHDL-FPGA-Verilog] 74-Hamming-code-encoder-and-decoder

Description: 基于VHDL实现（7，4）汉明码的编码器和译码器-VHDL-based implementation (7,4) Hamming code encoder and decoder
Platform: | Size: 3072 | Author: 付沅键 | Hits:

[VHDL-FPGA-Verilog] encoder

Description: 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Platform: | Size: 1024 | Author: Team | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。 -EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.
Platform: | Size: 797696 | Author: pear | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:

[VHDL-FPGA-Verilog] Priority-encoder

Description: 在Quartus II中用VHDL语言编写的优先级编码器程序-In the Quartus II VHDL language using the priority encoder program
Platform: | Size: 183296 | Author: 林燕 | Hits:

[Software Engineering] vhdl

Description: 3vhdl简单程序设计；4,8-3优先编码器5,3-8译码器；6,6d锁存器；7，数码管扫描显示；8，四位二进制加法计数器-3vhdl simple programming 4,8-3 5,3-8 priority encoder decoder 6,6 d latch 7, the digital scan 8, four binary up counter
Platform: | Size: 483328 | Author: 绿茶混咖啡 | Hits:

[VHDL-FPGA-Verilog] ug_rs-compiler

Description: altera RS编译码器datasheet-the datasheet of the rs encoder and decoder of altera
Platform: | Size: 413696 | Author: tangmin | Hits:

[VHDL-FPGA-Verilog] dvi_encoder_decoder_for---fpga

Description: dvi encoder and decoder in VHDL for FGPA developer.
Platform: | Size: 155648 | Author: Tran Thanh | Hits:

[VHDL-FPGA-Verilog] Encoder

Description: VHDL Beispiel für Encoder
Platform: | Size: 453632 | Author: sinp0915 | Hits:

[Other] encoder-bcd-counter

Description: the file of bcd counter, encoder vhdl code
Platform: | Size: 2048 | Author: park kyoung han | Hits:

[Modem program] encoder

Description: vhdl program for convolutional encoder and interleaver
Platform: | Size: 1024 | Author: nancy | Hits:

[VHDL-FPGA-Verilog] encoder

Description: 使用VHDL编写的光电编码器。并且在quartus软件进行仿真。最终下载在FPGA板上实现光电编码器的使用。-Optical encoder using VHDL written. And quartus software simulation. The final use of photoelectric encoder download FPGA board.
Platform: | Size: 4358144 | Author: 牛满 | Hits:

[VHDL-FPGA-Verilog] 7segment-display-VHDL

Description: 使用的NEXYS2原型设计电路板的7段编码器模拟-using the NEXYS 2 prototyping board Simulate the 7-segment encoder
Platform: | Size: 169984 | Author: Li Chen | Hits:

[Other] 8-3-Encoder

Description: VHDL program for “8:3 Encoder” behavioral design in Xilinx integrated software environment
Platform: | Size: 1024 | Author: rajapraba | Hits:

[Other] BCD-ENCODER

Description: VHDL program for “Decimal To BCD Encoder” behavioral design in Xilinx integrated software environment
Platform: | Size: 1024 | Author: rajapraba | Hits:

[Other] BIN-ENCODER

Description: VHDL program for “Octal To Binary Encoder” behavioral design in Xilinx integrated software environment
Platform: | Size: 1024 | Author: rajapraba | Hits:

[Other] PARITY-ENCODER

Description: VHDL program for “Parity Encoder” behavioral design in Xilinx integrated software environment
Platform: | Size: 1024 | Author: rajapraba | Hits:

[assembly language] VHDL

Description: 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
Platform: | Size: 119808 | Author: 陈增涛 | Hits:
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